The present invention relates to data processing systems, and more particularly to an improved method and apparatus for the communication between electronic devices to improve system cycle time, cost, and reliability. Modern high speed electronic systems often have chips of different internal voltage communicating with each other on a common bus. For example, because of intense competition in the microprocessor marketplace, there is great incentive for manufacturers to use the latest CMOS technology for the processor chip in order to achieve the highest possible clock frequency. However, the chips which provide memory and cache controller functions are often fabricated in the most cost effective technology, which is usually a generation or two behind the processor fabrication technology. In accordance with well established CMOS scaling principles, the supply voltage, Vdd, is being reduced as the chip minimum lithography dimension is made smaller. Thus, 5V technologies have been mostly supplanted by faster 3.3V CMOS chips with a 0.35-0.5 micron minimum dimension. The next generation of CMOS (0.2-0.25 micron) will use a Vdd of 2.5V, with future scaling of supply voltage to below 2V for subsequent generations of technology. Since it is best if all chips send and receive signals of the same voltage, this creates a problem. The common practice is to make all chips communicate at a ‘high’ voltage. For modern CMOS signals that would be either 3.3 or 5.0V. This creates several problems for chips with lower internal voltage.
One problem is increased delay and chip area due to the need for voltage translation circuits. Another problem is that even with translation circuits, the thin oxide layers of the transistors are stressed by the high external voltage, and are operating very close to the failure limit.
A similar problem that occurs is compatibility between chips of different internal voltages but the same or similar function. For example, it is now common practice in the computer industry to ‘remap’ a chip into a lower voltage, faster silicon technology. Thus a processor chip with a 3.3V internal voltage and a 0.4 micron gate length might be made with a more advanced silicon technology with a 2.5V internal voltage and a 0.25 micron gate length, with a resultant increase in operating frequency and a decrease in chip power. The problem is that the first processor can communicate easily with 3.3V SRAMs used for an external level 2 cache, but the 2.5V processor may have communication problems and voltage translation circuits may have to be used. Similarly SRAM's are ‘mapped’ into lower voltage. It is a likely scenario for both a processor and an SRAM to have 2.5V or even 1.8V internal voltage and be communicating with 3.3V external CMOS signals, with subsequent increased circuit cost, power, and delay. The higher external voltage can also cause decreased circuit reliability.
An alternative proposal is to have all chips communicate at a voltage lower than any internal voltage. An example is the 1.2V HSTL (High Speed Transceiver Logic) standard now before the Solid State Products Engineering Council (JEDEC) division of Electronic Industries Association (EIA). This method requires complex packaging for simple systems where all chips have the same voltage. Moreover the small signal swings of this low voltage interface can be too small for chips of high power, i.e., a 2.5V processor chip and a 1.2V interface, with coupled noise between the internal circuits and the interface circuits causing false data to appear on system busses. Nevertheless, there are times when such an interface is desired. It would be very helpful to have a means to switch between such a very low voltage interface, which requires a differential comparator type receiver and an externally supplied voltage reference VREF, and a standard CMOS interface which is best handled with a CMOS inverter as a receiver.
A previous invention by the authors, “VARIABLE VOLTAGE, VARIABLE IMPEDANCE CMOS OFF-CHIP DRIVER AND RECEIVER INTERFACE AND CIRCUITS”, filed as Ser. No. 08/598,084 in the United States, describes a variable voltage driver and receiver circuit, designed in CMOS, which can be used to send or receive CMOS signals (i.e., signals which swing between ground and the I/O voltage, VddQ) at various voltages, as long as VddQ<Vdd, the internal supply voltage. To accomplish this digital signals were used to vary properties of the driving and receiving circuit. Our new invention, described below, improves on this design by removing the requirement of digital controls for the driving circuit. Also, Ser. No. 08/598,084 could receive signals only through a CMOS inverter, i.e., it could not utilize the external reference voltage VREF described in recently approved JEDEC standards such as HSTL, GTL, CTT, and SSTL. Our new invention, described below, receives both CMOS signals through a CMOS inverter, or through a comparator circuit utilizing the VREF signal. This and more will be described below.